Firmware and embedded software engineers
Turn electrical events and system intent into deterministic, observable and recoverable behaviour on a constrained computing platform.
After this module, you should be able to:
- Structure firmware around explicit responsibilities and states
- Control concurrency, timing and shared resources
- Handle invalid inputs and faults deliberately
- Create reproducible implementation and verification evidence
Firmware is where logical decisions meet physical time.
The role spans boot, drivers, scheduling, control logic, diagnostics, communications, data storage and update. Correct results are not enough: they must arrive at the right time, in the right state and with predictable behaviour when inputs, hardware or execution fail.
Control behaviour from reset to recovery.
| Area | Key decision | Evidence |
|---|---|---|
| Boot and update | How are images authenticated, selected, rolled back and recovered? | Boot design and update tests |
| Concurrency | Who owns data and peripherals, and how is access bounded? | Task model and resource rules |
| Timing | What are the rates, deadlines, jitter limits and overload response? | Timing budget and measurements |
| State control | Which transitions are legal and what outputs accompany them? | State model and transition tests |
| Fault handling | What is detected locally, reported, retried or made safe? | Diagnostic design and fault tests |
Separate mechanism from policy
A driver should expose hardware truth and bounded operations; higher layers decide system policy. This makes behaviour testable and prevents safety decisions from being scattered across callbacks and interrupt handlers.
Build vertical slices before broad feature coverage.
- Define contracts. Record data representation, ownership, timing, errors and initial state.
- Establish the execution model. Map interrupts, tasks, priorities and blocking behaviour.
- Implement one end-to-end path. Sense, decide, actuate, report and diagnose.
- Add observability. Use structured events, counters, timestamps and retained fault context.
- Exercise adversity. Inject timeouts, corrupt data, resets and resource exhaustion.
- Automate the build. Pin tools, capture options and make artefacts reproducible.
Worked hand-off: missed control deadline
Systems engineering defines the latest safe output update. Firmware budgets execution and instruments deadline misses. Hardware provides a watchdog or output-disable path. Safety engineering defines the required reaction, while verification drives CPU and I/O load to demonstrate the response.
Keep implementation intent and results reproducible.
Components, dependencies, data flow and execution model.
Hardware registers, messages, timing and error semantics.
Reviews, static analysis, coding rules and traceable changes.
Tool versions, options, dependencies and binary identity.
Measured load, latency, stack use and worst observed cases.
Unit, integration, target and fault-injection outcomes.
Common traps
Control policy becomes hidden in asynchronous side effects.
Timeout, partial transfer and peripheral reset are ignored.
Logical assertions pass while deadlines remain unverified.
The released image cannot be rebuilt from controlled inputs.
Further learning
- Arm CMSIS documentationProcessor, device and software interfaces for Cortex-based systems.
- TEA-105 · Real-time behaviourTiming, scheduling and concurrency foundations.
Engineer the behaviour around the code.
Dependable firmware makes ownership, states, timing, diagnostics and recovery as deliberate as the functional algorithm.