Microcontrollers and peripherals
Treat the MCU as an integrated platform—not simply a processor—and select its core, memory and peripherals against the complete system need.
After this module, you should be able to:
- Explain how the core, memory and peripherals cooperate
- Select an MCU using system-level criteria
- Reason about interrupts, timers and DMA
- Identify configuration and lifecycle evidence to retain
A microcontroller is a coordinated collection of resources.
An MCU combines a processor core, programme and data memory, clock and reset control, interrupt handling, input / output and specialised peripherals on one device. Much of the system’s real-time behaviour comes from how these resources are configured and connected—not from instruction speed alone.
Peripherals can often perform work autonomously. A timer can trigger an ADC; DMA can transfer samples into memory; a comparator can shut down a PWM output without waiting for software. Used deliberately, these paths reduce latency and processor loading. Used casually, they create hidden behaviour that is difficult to analyse and test.
Select for the worst credible operating condition.
| Dimension | Questions to ask | Common trap |
|---|---|---|
| Compute | Worst-case execution time, interrupt loading, control rate, start-up time and future margin? | Using average CPU load as proof |
| Memory | Code, stacks, heaps, buffers, diagnostics, update image and growth allowance? | Counting only the current application binary |
| Peripherals | Channels, simultaneous use, resolution, trigger routes, pin conflicts and electrical limits? | Assuming every advertised function can operate together |
| Timing | Clock accuracy, timer width, capture resolution, interrupt latency and jitter? | Equating clock frequency with determinism |
| Safety and security | Watchdogs, memory protection, ECC, self-test, secure boot, key storage and debug control? | Adding protection after hardware selection |
| Power and environment | Modes, wake sources, voltage, temperature, EMC sensitivity and thermal dissipation? | Using headline low-power figures |
| Lifecycle | Availability, second source, errata, toolchain support and migration route? | Ignoring obsolescence and silicon revisions |
Check pin multiplexing and shared resources early
Two required peripherals may need the same pin, DMA channel, interrupt vector, clock source or bus bandwidth. Build a resource-allocation table while the schematic and architecture can still change.
Understand the paths that create timing behaviour.
Interrupts
An interrupt turns an asynchronous event into processor execution. Define priority, maximum service time, permitted nesting, shared-data protection and the consequence of an event arriving faster than it can be handled. Keep interrupt service routines bounded and move non-urgent work to a controlled execution context.
Timers and capture / compare
Timers create precise periods, timestamps, pulse measurements and PWM signals. Their resolution depends on source clock, prescaling and counter width. Rollover, synchronisation and clock changes must be designed rather than discovered during test.
Direct memory access
DMA moves data without an instruction for every transfer, but it introduces concurrent access to memory and peripherals. Specify buffer ownership, completion signalling, coherency, overrun behaviour and recovery from transfer errors.
Worked example: sampled motor control
A strong design identifies which path is normal and which path provides rapid protection. The control task may update PWM at 1 kHz, while a hardware fault input disables the output within microseconds. The slower software path must not be credited with the faster hardware response.
Configuration is part of the product design.
Clock trees, option bytes, pin modes, interrupt priorities, watchdog windows and peripheral registers materially affect behaviour. Generated configuration files are useful, but the design still needs human-readable intent and verification.
System requirements, margins, alternatives, safety / security features and lifecycle considerations.
Pins, timers, buses, interrupts, DMA channels, memory and clock domains.
Tool version, generated files, option settings, device revision and controlled changes.
Interrupt load, worst-case paths, deadlines, latency and jitter measurements.
Applicable silicon issues, impact, workarounds and verification.
Clock, reset, memory, watchdog, communications and peripheral boundary tests.
Common failure patterns
“Has ADC” says nothing about accuracy, speed, reference, trigger, channel interaction or usable pins.
A configuration tool silently changes clocks, priorities or initialisation order.
Timing is assessed in isolation rather than with simultaneous worst-case sources.
The chosen silicon revision has a limitation that invalidates a credited behaviour.
Further learning
- Microchip microcontroller overviewExamples of MCU cores, integrated peripherals and application-oriented selection.
- Arm CMSIS documentationStandardised access to processor cores, peripherals, drivers, RTOS interfaces and debug.
Select and control the whole MCU platform.
Dependable behaviour comes from the combined design of core, memory, clocks, interrupts and peripherals—including their shared resources, configuration and failure responses.